The present invention relates to semiconductor storage devices such as a normal mask ROM and a page mode mask ROM.
Conventionally, as a semiconductor storage device, there has been a general-purpose normal mask ROM that operates in accordance with the control timing shown in FIGS. 17A through 17I. As shown in FIGS. 17A through 17I, this normal mask ROM executes precharging (shown in FIG. 17C) of the desired bit line and virtual GND line decoded by a column address simultaneously with the turn on of the word line (shown in FIG. 17B) after the input of a row address and a column address. If an equalizing operation of the bit line and the reference line is required and a lot of memory cells are connected to one bit line, then the precharge operation and the equalizing operation of the bit line and the virtual GND line are executed taking a time being about two times the word line turn on time. After the completion of the precharge operation and the equalizing operation, a bit line sensing operation is executed by the memory cell. This bit line sensing operation means a bit line drawing operation for drawing in the potential of the bit line by the memory cell. The potential of the bit line is lowered in the case where the transistor of the memory cell is on (referred to as an ON-state transistor hereinafter), and the precharge potential of the bit line is maintained in the case where the transistor of the memory cell is off (referred to as an OFF-state transistor hereinafter) (shown in FIGS. 17E and 17H). Next, a potential difference between the bit line and the reference line, generated through this bit line sensing operation of the memory cell, is amplified by a sense amplifier (not shown), and the resulting data is outputted via an output buffer (not shown).
As described above, in the case of the normal mask ROM having a random access function, the row address and the column address are simultaneously inputted so as to execute parallel the turn on of the desired word line and the precharge operation and the equalizing operation of the desired bit line.
There is another semiconductor storage device as shown in FIG. 18 (refer to the prior art reference of Japanese Patent Laid-Open Publication No. HEI 6-139787). The control timing of the above semiconductor storage device is shown in FIG. 19.
In FIG. 18 are shown a memory cell MC, a dummy memory cell DMC, precharge transistors PC and DPC, a word line WL, a precharge signal line /PR, a bit line BL, a dummy bit line DBL, a level detecting circuit 132 and a data output circuit 133. A decoding signal WD is inputted to one input terminal of a two-input NOR circuit 130 via an inverter 141, while a DE signal is inputted from the level detecting circuit section 132 to the other input terminal of the two-input NOR circuit 130. An output terminal of the two-input NOR circuit 130 is connected to the word line WL. A clock signal CLK is inputted to one input terminal of a two-input NOR circuit 131, while the DE signal is inputted to the other input terminal of the two-input NOR circuit 131. The output terminal of the two-input NOR circuit 131 is connected to the precharge signal line /PR. The level detecting circuit section 132 is constructed of inverters 135 and 136, a flip-flop circuit 134, a two-input NAND circuit 143 and an inverter 144. The data output circuit section 133 is constructed of inverters 137 and 138 and a flip-flop circuit 139.
In the semiconductor storage device having the above construction, as shown in FIGS. 19A through 19H, by providing a period during which the clock signal CLK (shown in FIG. 19A) comes to have H-level (high level) and making the precharge signal line /PR (shown in FIG. 19B) have L-level (low level), the transistors PC and DPC are turned on to execute the precharging of the bit line BL and the dummy bit line DBL (shown in FIGS. 19E and 19F).
Next, the potential of the selected word line WL (shown in FIG. 19D) rises to turn on the memory cell transistor MC and the dummy memory cell transistor DMC, executing the sensing of the bit line BL and the dummy bit line DBL by the memory cell transistor MC and the dummy memory cell transistor DMC, respectively.
Subsequently, if the potential of the bit line BL becomes lower than a circuit threshold value of an inverter 137 provided inside the data output circuit section 133, then the output of the inverter 137 is amplified to H-level, and the inverter 138 outputs L-level. Then, the output of the inverter 138 is latched in the latch circuit 139, making an output signal Dout have L-level (shown in FIG. 19H).
The sensing of the dummy bit line DBL is executed by the dummy memory cell transistor DMC, and therefore, the potential of the dummy bit line DBL is also lowered similarly to the potential of the bit line BL.
Subsequently, if the potential of the dummy bit line DBL becomes lower than the circuit threshold value of the inverter 135 provided inside the level detecting circuit section 132, then the output of the inverter 135 is amplified to H-level, and a power voltage Vcc is inputted as data into the flip-flop circuit 134, changing the level of the output signal DE from L-level to H-level (shown in FIG. 19G).
If the level of the output signal DE changes to H-level, then the output of the two-input NOR circuit 130 to which the output signal DE is inputted comes to have L-level, as a consequence of which the memory cell transistor MC and the dummy memory cell transistor DMC are turned off. The output signal /PR of the two-input NOR circuit 131 to which the output signal DE is inputted also comes to have L-level to turn on the precharge transistors PC and DPC, consequently precharging the bit line BL and the dummy bit line DBL, respectively.
In the semiconductor storage device having the construction shown in FIG. 18, the precharge timing is also automatically changed depending on the load capacitance of the bit line when designing a memory of a variety of sizes required for a memory of ASIC (application-specific integrated circuit) or the like, and therefore, the circuit designing can be easily achieved.
In the normal mask ROM controlled in accordance with the timing shown in FIG. 17, the bit line load is increased when a lot of memory cells are connected to the bit line, and the time necessary for the precharge operation and the equalizing operation of the bit line and the virtual GND line as well as the bit line sensing operation by the memory cell occupies about fifty percent of the access time. Some devices have the time two or more times greater than the time required for the turn on of the word line. If a small number of memory cells are connected to the bit line, then the time necessary for the precharge operation and the equalizing operation of the bit line and the virtual GND line as well as the bit line sensing operation by the memory cell occupies about thirty percent of the access time. There is an attempt at reducing the load of the bit line by dividing the bit line for the purpose of increasing the access time speed, for the reduction of the time necessary for the precharge operation and the equalizing operation. However, according to the system in which the bit line is divided, there is resulting an increased number of precharge circuits, sense amplifiers and column decoders, and this incurs a significant increase in chip size.
The semiconductor storage device shown in FIG. 18 detects a reduction in level of DBL and then enters into the bit line precharge operation. Another embodiment of the same prior art reference detects a change in potential of the read data and then enters into the precharge operation. These cases require a means for detecting the reduction in level of DBL and the change in output potential.